Design & Verification Engineer (Embedded System) - Work in Japan.

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Aussicht: 153

Update Tag: 14-04-2024

Ort: Vietnam International

Kategorie: Elektrik / Elektronik IT - Software Mechanische / Technische

Position: Nhân viên

Gehalt: 2,000 USD - 2,500 USD

Bildung: Cử nhân

Sex: Nam / Nữ

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Jobbeschreibung

- Reciving order by specification of function and specification of mouting on circuit .

- Designing and programming according specification and confiring the verification.

- Programing by Verilog/System Verilog for RTL or by SystemC/C/C++ for high-level synthesis.

- Verifying environment construction & scenario in SystemVerilog/SVA/UVM/C.

*** Working day & time: Mon - Fri, 8:30～17:30 (Flexitime system - core time - 10:00~15:00).

*** Working place: Dist. 3 (3 months) & Tokyo, Japan.

*** Benefit:

- Bonus : 2 time per year.

- Lunch allowance.

- Commuting allowance.

- Child allowance (women)

- Long-term service allowance (5 years or more)

- Travel allowance (domestic/overseas)

- Company trip.

- Language/technical acquisition allowance.

- Individual insurance support.

- Company uniform.

Stellenanforderung

- Graduated from electronic related majors.

- Having experience of using verilog over 2 years.

- Can communicate English.

- Having knowledge of Synopsys / Cadence.

- Can go to Japan 1~2 years.

- Better: Can communicate in Japanese.

Kontaktinformation

Kontakt: Ms. Hạnh Thảo

Adresse: Phòng 302, Tòa Nhà NK, 270-272 Cộng Hòa, P.13 , Quận Tân Bình , Hồ Chí Minh , Viet Nam

Frist: 14-05-2024

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